Typically, 1T-1C (one capacitor and one capacitor) type DRAMs have been used. Instead of the 1T-1C type DRAMs, 2T-2C (two transistors and two capacitors) type DRAMs may be used. The 2T-2C type DRAM has the disadvantage that its memory cell area is large, while having the advantage that, its memory cell sensing margin is almost double the memory cell sensing margin of the IT-1C type DRAM cell because complementary data is stored in one DRAM cell, and a reference voltage for a bitline sense amplifier is unnecessary.
A 2T-2C type DRAM unit cell is now described below with reference to FIG. 1 and FIG. 2.
Referring to FIG. 1, a conventional 2T-2C type DRAM unit cell 100 is illustrated. A first cell transistor 101 has a gate coupled to a wordline WL, a drain coupled to a bitline BL, and a source coupled to one electrode of a first cell transistor 102. The other electrode of the first cell capacitor 102 is coupled to a plate line PL. A second cell transistor 103 has a gate coupled to the wordline WL, a drain coupled to a complementary bitline BLB, and a source coupled to one electrode of a second cell capacitor 104. The other electrode of the second cell capacitor 104 is coupled to the plate line PL. The first cell transistor 101 and the fist cell capacitor 102 constitute a memory cell CELL, and the second cell transistor 103 and the second cell capacitor 104 constitute a complementary memory cell CELLB. Accordingly, data stored in the first cell capacitor 102 is complementary with data stored in the second cell capacitor 104.
Referring to FIG. 2, another conventional 2T-2C type DRAM unit cell 200 is illustrated. A first cell transistor 201 and a first cell capacitor 202 and a second cell transistor 203 and a second cell capacitor 204 are reflected with respect to a plate PL.
The DRAM cells 100 and 200 are copied or reflected in the row (or wordline) direction or the column (or bitline) direction to be disposed in a memory cell block.
Ferroelectric random access memory (FRAM) may be variously configured with memory cells. FIG. 3 and FIG. 4 illustrate 2T-2C type FRAM cells 300 and 400 which are similar to the 2T-2C type DRAM cells 100 and 200, respectively. A first ferroelectric capacitor 302 coupled to a first cell transistor 301 and a second ferroelectric capacitor 304 coupled to a second cell transistor 303 are magnetized with opposite polarity. The FRAM cell connection structures of FIG. 1 and FIG. 2 are identical with those of FIG. 3 and FIG. 4, respectively.
FIG. 5 illustrates a memory array 500 including the same unit cells as shown in FIG. 2 or FIG. 4. First to eighth memory cells MCi (i=0, 1, . . . , 7) coupled to a first wordline WL0 and ninth to sixteenth memory cells MCi (i=8, 9, . . . , 15) coupled to a second wordline WL1 are connected to sense amplifiers (S/A) 501, 502, 503, and 504 through bitlines BLi (i=0, 1, 2, 3) and complementary bitline BLiB (i=0, 1, 2, 3). First and third bitline/complementary bitline couples BL0/BL0B and BL2/BL2B are connected to the sense amplifiers 501 and 503 over the memory cell array, respectively. Second and fourth bitline/complementary bitline couples BL1/BL1B and BL3/BL3B are connected to the sense amplifiers 502 and 504 disposed under the memory cell array, respectively.
As the memory capacity increase, arranged memory cells as well as sense amplifiers increase in number. Thus a layout area occupied by the sense amplifies increases and the sense amplifiers are densely populated, which makes it difficult to perform an integration process. In addition, power consumption increases along with increase in number of the arranged sense amplifiers because they operate at the same time. Accordingly, there is a demand for a memory device having a memory block arrangement which can reduce chip size and power consumption.